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| author | Alex Zinenko <zinenko@google.com> | 2020-01-17 18:16:07 +0100 |
|---|---|---|
| committer | Alex Zinenko <zinenko@google.com> | 2020-01-17 18:20:24 +0100 |
| commit | f343544b813891387add8ef01406d36b82ed0a7e (patch) | |
| tree | 4ca3735ed321e00b07705b2138f9fdd1d7940514 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | b9d2bf38e86e6dd8a2f188d9a24f546aa67de8af (diff) | |
| download | llvm-f343544b813891387add8ef01406d36b82ed0a7e.zip llvm-f343544b813891387add8ef01406d36b82ed0a7e.tar.gz llvm-f343544b813891387add8ef01406d36b82ed0a7e.tar.bz2 | |
[mlir] Generator converting LLVM intrinsics defs to MLIR ODS
Introduce a new generator for MLIR tablegen driver that consumes LLVM IR
intrinsic definitions and produces MLIR ODS definitions. This is useful to
bulk-generate MLIR operations equivalent to existing LLVM IR intrinsics, such
as additional arithmetic instructions or NVVM.
A test exercising the generation is also added. It reads the main LLVM
intrinsics file and produces ODS to make sure the TableGen model remains in
sync with what is used in LLVM.
Differential Revision: https://reviews.llvm.org/D72926
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions