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| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-04-05 16:42:32 +0000 |
|---|---|---|
| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-04-05 16:42:32 +0000 |
| commit | efc3f39f0293c930dd228cc43ce8c087795476b1 (patch) | |
| tree | d2ea489b3d0a39e4ecdc069f3a58f4455db05fbf /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 6ecdb03f16b7e521c7f07677e2314631cb066244 (diff) | |
| download | llvm-efc3f39f0293c930dd228cc43ce8c087795476b1.zip llvm-efc3f39f0293c930dd228cc43ce8c087795476b1.tar.gz llvm-efc3f39f0293c930dd228cc43ce8c087795476b1.tar.bz2 | |
[documentation][llvm-mca] Update the documentation.
Scheduling models can now describe processor register files and retire control
units. This updates the existing documentation and the README file.
llvm-svn: 329311
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions