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| author | Momchil Velikov <momchil.velikov@arm.com> | 2024-01-11 14:47:32 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-01-11 14:47:32 +0000 |
| commit | ef4a95c86210e11cf4bfbf545c2f859b5c772888 (patch) | |
| tree | 865b76674fad86751518a325cd4b17de198bf525 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 13b5882ee64b7aa6ee08900b7b2f0cc2cbc37f53 (diff) | |
| download | llvm-ef4a95c86210e11cf4bfbf545c2f859b5c772888.zip llvm-ef4a95c86210e11cf4bfbf545c2f859b5c772888.tar.gz llvm-ef4a95c86210e11cf4bfbf545c2f859b5c772888.tar.bz2 | |
[AArch64] Enable certain instruction aliases for SVE/SME (#77745)
Several SVE instruction aliases accept predicate-as-counter register
names as a convenience. These ought to be enabled with SVE/SME because
the underlying encoding is valid and it's required by Arm ARM.
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions