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| author | Dhruv Chauhan <dhruv.chauhan@arm.com> | 2023-10-18 11:38:35 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-10-18 11:38:35 +0100 |
| commit | c92629150e361f7b2a06fc56200389b727616411 (patch) | |
| tree | a38163dc5458918dad9e4f2fd01a1966fba436c0 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 0dca56603b4e13232dfb1f1b80e01604fcf36314 (diff) | |
| download | llvm-c92629150e361f7b2a06fc56200389b727616411.zip llvm-c92629150e361f7b2a06fc56200389b727616411.tar.gz llvm-c92629150e361f7b2a06fc56200389b727616411.tar.bz2 | |
[MLIR][TOSA] Fix f16/bf16 support for MaxPool2D (#69332)
Currently, the MaxPool2D operation in the TOSA MLIR dialect does not
accept half-precision Fp16 and Bf16 tensors, converse to what is stated
in the [TOSA
Specification](https://www.mlplatform.org/tosa/tosa_spec.html#_max_pool2d).
This patch fixes the verifier to accept the two datatypes for
input/output tensors, and adds related LIT test cases in Tosa/ops.mlir
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions