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| author | Jessica Paquette <jpaquette@apple.com> | 2021-09-14 10:03:42 -0700 |
|---|---|---|
| committer | Jessica Paquette <jpaquette@apple.com> | 2021-09-15 17:05:09 -0700 |
| commit | c8b3d7d6d6de37af68b2f379d0e37304f78e115f (patch) | |
| tree | d74fb316d92e24ac20d2fec8706a21d1c789c182 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | e159d3cbfc250115d1244f3a6219436a52f90f86 (diff) | |
| download | llvm-c8b3d7d6d6de37af68b2f379d0e37304f78e115f.zip llvm-c8b3d7d6d6de37af68b2f379d0e37304f78e115f.tar.gz llvm-c8b3d7d6d6de37af68b2f379d0e37304f78e115f.tar.bz2 | |
[AArch64][GlobalISel] Ensure atomic loads always get assigned GPR destinations
The default register bank selection code for G_LOAD assumes that we ought to
use a FPR when the load is casted to a float/double.
For atomics, this isn't true; we should always use GPRs.
Without this patch, we crash in the following example:
https://godbolt.org/z/MThjas441
Also make the code a little more stylistically consistent while we're here.
Also test some other weird cast combinations as well.
Differential Revision: https://reviews.llvm.org/D109771
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions