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| author | Craig Topper <craig.topper@sifive.com> | 2020-11-25 09:43:16 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2020-11-25 10:01:47 -0800 |
| commit | c26e8697d71eea5fa08944a2db039a2187abf27c (patch) | |
| tree | cd65312178ab839f953e352fc45202fccc17a7e0 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 227c8ff189c3861c11f6e80c31274c5fa28a2ee9 (diff) | |
| download | llvm-c26e8697d71eea5fa08944a2db039a2187abf27c.zip llvm-c26e8697d71eea5fa08944a2db039a2187abf27c.tar.gz llvm-c26e8697d71eea5fa08944a2db039a2187abf27c.tar.bz2 | |
[RISCV] Custom type legalize i32 fshl/fshr on RV64 with Zbt.
This adds custom opcodes for FSLW/FSRW so we can type legalize
fshl/fshr without needing to match a sign_extend_inreg.
I've used the operand order from fshl/fshr to make the isel
pattern similar to the non-W form. It was also hard to decide
another order since the register instruction has the shift amount
as the second operand, but the immediate instruction has it as
the third operand.
Differential Revision: https://reviews.llvm.org/D91479
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions