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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-12-31 15:28:41 -0500 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-01-15 08:58:58 -0500 |
| commit | bd7658a212ebc27a8f7d69666820df33bc8d61f5 (patch) | |
| tree | 637ce5c15ff6f600624a91cc16d8ace46fa3f3cb /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 91715617ad601c6bd953e1c47ecaaf3610de233f (diff) | |
| download | llvm-bd7658a212ebc27a8f7d69666820df33bc8d61f5.zip llvm-bd7658a212ebc27a8f7d69666820df33bc8d61f5.tar.gz llvm-bd7658a212ebc27a8f7d69666820df33bc8d61f5.tar.bz2 | |
AMDGPU: Partially directly select llvm.amdgcn.interp.p1.f16
The 16 bank LDS case is complicated due to using multiple
instructions. If I attempt to write a pattern for it, the generated
selector incorrectly places the copy to m0 after the first
instruction, so that needs to be separately addressed.
Also fix not gluing the copy to m0 to the second operation in the
second half of the 16 bank lowering.
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions