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| author | Chris Lattner <sabre@nondot.org> | 2009-03-13 16:25:21 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2009-03-13 16:25:21 +0000 |
| commit | ba42e49c14abcb513672efa6cb8579731894764b (patch) | |
| tree | 9b9375a23e9b7edf3184fa79378e0771967e0824 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | bd9b9210c23505931e261f71588437a4818d5ddb (diff) | |
| download | llvm-ba42e49c14abcb513672efa6cb8579731894764b.zip llvm-ba42e49c14abcb513672efa6cb8579731894764b.tar.gz llvm-ba42e49c14abcb513672efa6cb8579731894764b.tar.bz2 | |
add a new TGError class and use it to propagate location info with
errors when thrown. This gets us nice errors like this from tblgen:
CMOVL32rr: (set GR32:i32:$dst, (X86cmov GR32:$src1, GR32:$src2))
/Users/sabre/llvm/Debug/bin/tblgen: error:
Included from X86.td:116:
Parsing X86InstrInfo.td:922: In CMOVL32rr: X86cmov node requires exactly 4 operands!
def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
^
instead of just:
CMOVL32rr: (set GR32:i32:$dst, (X86cmov GR32:$src1, GR32:$src2))
/Users/sabre/llvm/Debug/bin/tblgen: In CMOVL32rr: X86cmov node requires exactly 4 operands!
This is all I plan to do with this, but it should be easy enough to improve if anyone
cares (e.g. keeping more loc info in "dag" expr records in tblgen.
llvm-svn: 66898
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions
