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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-10-23 15:45:43 -0400 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-10-28 12:02:16 -0400 |
| commit | b9c21d43bb0c9e1a6d51f624f4369c717516a459 (patch) | |
| tree | ed686f3d24e056724bcf313093147af738a79e37 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 09c73456837a76a8496edf42732f6e47b35a2bb5 (diff) | |
| download | llvm-b9c21d43bb0c9e1a6d51f624f4369c717516a459.zip llvm-b9c21d43bb0c9e1a6d51f624f4369c717516a459.tar.gz llvm-b9c21d43bb0c9e1a6d51f624f4369c717516a459.tar.bz2 | |
RegAlloc: Clear isSSA
The MIR parser may infer SSA, so -run-pass=regallocgreedy would hit a
verifier error after multiple vreg defs are added.
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions