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| author | Sergey Kachkov <sergey.kachkov@syntacore.com> | 2023-01-25 16:10:29 +0300 |
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| committer | Sergey Kachkov <sergey.kachkov@syntacore.com> | 2023-02-27 12:08:15 +0300 |
| commit | b5bf6f6392a3408be1b7b7e036eb69358c5a2c29 (patch) | |
| tree | 7f7e3b0afad17a57121b339cdc8aba88fc18b0c9 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | d9391a37a9f8eb222a951606e0ca5d6a5b6b2199 (diff) | |
| download | llvm-b5bf6f6392a3408be1b7b7e036eb69358c5a2c29.zip llvm-b5bf6f6392a3408be1b7b7e036eb69358c5a2c29.tar.gz llvm-b5bf6f6392a3408be1b7b7e036eb69358c5a2c29.tar.bz2 | |
[GVN] Support address translation through select instructions
Process cases when phi incoming in predecessor block has select
instruction, and this select address is unavailable, but there
are addresses translated from both sides of select instruction.
Differential Revision: https://reviews.llvm.org/D142705
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions