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| author | Igor Breger <igor.breger@intel.com> | 2017-08-20 07:14:40 +0000 |
|---|---|---|
| committer | Igor Breger <igor.breger@intel.com> | 2017-08-20 07:14:40 +0000 |
| commit | b3a860a5e89bff8e65aba7af534d6c23668ebe24 (patch) | |
| tree | b631e35b7eb9df11095e5d083e294a8d0725e3a2 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 21c8adf50b3a15af6a515763cc0c97f42d663a67 (diff) | |
| download | llvm-b3a860a5e89bff8e65aba7af534d6c23668ebe24.zip llvm-b3a860a5e89bff8e65aba7af534d6c23668ebe24.tar.gz llvm-b3a860a5e89bff8e65aba7af534d6c23668ebe24.tar.bz2 | |
[GlobalISel][X86] Support asimetric copy from/to GPR physical register.
Usually this case generated by ABI lowering, it requare to performe trancate/anyext.
llvm-svn: 311278
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions