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author | Thomas Lively <tlively@google.com> | 2021-08-19 15:24:28 -0700 |
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committer | Thomas Lively <tlively@google.com> | 2021-08-19 15:24:28 -0700 |
commit | b311a040ef9cda6d52fdfdd4968f2dc59ccf596e (patch) | |
tree | b282a690e8e2355bc2d2a14692bbf2532b61e41c /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
parent | 898dc4590c4fcf230531be7f9a0099632e8af78c (diff) | |
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[WebAssembly] Pattern match SIMD convert_low and promote_low during ISel
Since the simplest DAG patterns for convert_low and promote_low instructions
involved v2i32, v2f32, v4i64, and v4f64 types, which are not legal in the
WebAssembly backend and would be eliminated by type legalization, we were
previously matching those patterns in a DAG combine before the type legalization
stage. However in cases where the vectors were wider than 128 bits, the patterns
we matched were not created until the type legalization stage when the wide
vectors were split up. Type legalization would continue to eliminate the illegal
types we were matching as well, so the code ended up scalarized.
To make the ISel for these instructions more robust, match the scalarized
patterns rather than the patterns containing illegal types. Add tests with
double-wide vectors to show that this works as intended.
Fixes PR51098.
Depends on D107502.
Differential Revision: https://reviews.llvm.org/D108266
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
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