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| author | Piotr Fusik <p.fusik@samsung.com> | 2025-06-04 17:32:40 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-06-04 17:32:40 +0200 |
| commit | afa517a3c2b21b366e60a6fd16b5f96e5e8a9f0c (patch) | |
| tree | ccda0daba36bf74baa6a4acc0a7576a14046ec8e /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 07a534160a7c500cb71425344cca223cadd9b938 (diff) | |
| download | llvm-afa517a3c2b21b366e60a6fd16b5f96e5e8a9f0c.zip llvm-afa517a3c2b21b366e60a6fd16b5f96e5e8a9f0c.tar.gz llvm-afa517a3c2b21b366e60a6fd16b5f96e5e8a9f0c.tar.bz2 | |
[RISCV] Fold SRLIW+SLLI+ADD into SRLIW+SHXADD (#142611)
This handles RV64 SRLIW, similarly to SRLI.
Also fixing the comments for SRLI combines that did not match the code.
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions