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| author | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2020-02-20 17:42:51 -0800 |
|---|---|---|
| committer | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2020-03-03 16:41:09 +0100 |
| commit | ae4d39c9e4ad391b817a798aa4b5fecfbe9c6cf4 (patch) | |
| tree | f219e596ffa8e311dc65956146fcbd85bc0b537c /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 573e0776996425dd0567448d4a1f805a1f613e6d (diff) | |
| download | llvm-ae4d39c9e4ad391b817a798aa4b5fecfbe9c6cf4.zip llvm-ae4d39c9e4ad391b817a798aa4b5fecfbe9c6cf4.tar.gz llvm-ae4d39c9e4ad391b817a798aa4b5fecfbe9c6cf4.tar.bz2 | |
[SystemZ] Copy Access registers and CC with the correct register class.
On SystemZ there are a set of "access registers" that can be copied in and
out of 32-bit GPRs with special instructions. These instructions can only
perform the copy using low 32-bit parts of the 64-bit GPRs. However, the
default register class for 32-bit integers is GRX32, which also contains the
high 32-bit part registers.
In order to never end up with a case of such a COPY into a high reg, this
patch adds a new simple pre-RA pass that selects such COPYs into target
instructions.
This pass also handles COPYs from CC (Condition Code register), and COPYs to
CC can now also be emitted from a high reg in copyPhysReg().
Fixes: https://bugs.llvm.org/show_bug.cgi?id=44254
Review: Ulrich Weigand.
Differential Revision: https://reviews.llvm.org/D75014
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions