diff options
| author | Oliver Stannard <oliver.stannard@arm.com> | 2024-11-13 13:16:28 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-13 12:16:28 +0000 |
| commit | aba55809e9af5e0d981f10c7f9b44a1f57b423c2 (patch) | |
| tree | 4e04c25a5fc37484921163a7c58e51153b0923de /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 856c47b884ada7dadb1081244821e0acc199cc72 (diff) | |
| download | llvm-aba55809e9af5e0d981f10c7f9b44a1f57b423c2.zip llvm-aba55809e9af5e0d981f10c7f9b44a1f57b423c2.tar.gz llvm-aba55809e9af5e0d981f10c7f9b44a1f57b423c2.tar.bz2 | |
[ARM] Fix operand order for MVE predicated VFMAS (#115908)
For most MVE predicated FMA instructions, disabled lanes will contain
the value in the addend operand. However, The VFMAS instruction takes
the addend in a GPR, and the output register is shared with the first
multiply operand, so disabled lanes will get that value instead. This
means that we can't use the same intrinsic as for the other VFMA
instructions. Instead, we can codegen the vfmas intrinsic to a regular
FMA and select in clang, which the backend already has the patterns to
select VFMAS from.
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions