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author | Craig Topper <craig.topper@sifive.com> | 2021-09-27 09:45:30 -0700 |
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committer | Craig Topper <craig.topper@sifive.com> | 2021-09-27 09:54:46 -0700 |
commit | a2a07e8db3bf64440f24d9d6408df214886826de (patch) | |
tree | 332c1284f99df8b22741843041483909ccbca0af /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
parent | 2bf06d9345caeb26520be8e830c092683bbdf0f7 (diff) | |
download | llvm-a2a07e8db3bf64440f24d9d6408df214886826de.zip llvm-a2a07e8db3bf64440f24d9d6408df214886826de.tar.gz llvm-a2a07e8db3bf64440f24d9d6408df214886826de.tar.bz2 |
[RISCV] Fold store of vmv.x.s to a vse with VL=1.
This can avoid a loss of decoupling with the scalar unit on cores
with decoupled scalar and vector units.
We should support FP too, but those use extract_element and not a
custom ISD node so it is a little different. I also left a FIXME
in the test for i64 extract and store on RV32.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D109482
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
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