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| author | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2016-05-16 08:57:59 +0000 |
|---|---|---|
| committer | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2016-05-16 08:57:59 +0000 |
| commit | 973405bec5b6f5594bc9d1e96ec62c00cf69bd7a (patch) | |
| tree | ab6fbb314c5971d81eec0e799c4c8635028382bf /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | f606c8d633e288a7d2ac95f7372af374dcab7f39 (diff) | |
| download | llvm-973405bec5b6f5594bc9d1e96ec62c00cf69bd7a.zip llvm-973405bec5b6f5594bc9d1e96ec62c00cf69bd7a.tar.gz llvm-973405bec5b6f5594bc9d1e96ec62c00cf69bd7a.tar.bz2 | |
[mips] Addition of a third operand to the instructions [d]div, [d]divu
Author: obucina
Reviewers: dsanders
Adds support for third operand for [D]DIV[U] instructions. Additional test for case when destination reg is zero register
Differential Revision: http://reviews.llvm.org/D16888
llvm-svn: 269636
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions