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author | Amara Emerson <amara@apple.com> | 2021-08-18 00:19:58 -0700 |
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committer | Amara Emerson <amara@apple.com> | 2021-08-19 16:38:52 -0700 |
commit | 95ac3d15e9fe86d9b51b51d02cb3c1640bf30dee (patch) | |
tree | eb928600c2d369838959eb0ada71055ff07e0dcb /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
parent | fbb8e772ec501a1b71643db90e9c6445e17d7cac (diff) | |
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[AArch64][GlobalISel] Add G_VECREDUCE fewerElements support for full scalarization.
For some reductions like G_VECREDUCE_OR on AArch64, we need to scalarize
completely if the source is <= 64b. This change adds support for that in
the legalizer. If the source has a pow-2 num elements, then we can do
a tree reduction using the scalar operation in the individual elements.
Otherwise, we just create a sequential chain of operations.
For AArch64, we only need to scalarize if the input is <64b. If it's great than
64b then we can first do a fewElements step to 64b, taking advantage of vector
instructions until we reach the point of scalarization.
I also had to relax the verifier checks for reductions because the intrinsics
support <1 x EltTy> types, which we lower to scalars for GlobalISel.
Differential Revision: https://reviews.llvm.org/D108276
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
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