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| author | Cullen Rhodes <cullen.rhodes@arm.com> | 2020-05-28 09:37:55 +0000 |
|---|---|---|
| committer | Cullen Rhodes <cullen.rhodes@arm.com> | 2020-05-28 10:02:57 +0000 |
| commit | 8a397b66b2c672999e9e6d63334d5bffd7db1a3f (patch) | |
| tree | d918a53ff09493a5ce98335f28e89b17ee26750e /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | c010d4d195506aaea76a1cc8afb5a6b5884dba44 (diff) | |
| download | llvm-8a397b66b2c672999e9e6d63334d5bffd7db1a3f.zip llvm-8a397b66b2c672999e9e6d63334d5bffd7db1a3f.tar.gz llvm-8a397b66b2c672999e9e6d63334d5bffd7db1a3f.tar.bz2 | |
[AArch64][SVE] Add support for spilling/filling ZPR2/3/4
Summary:
This patch enables the register allocator to spill/fill lists of 2, 3
and 4 SVE vectors registers to/from the stack. This is implemented with
pseudo instructions that get expanded to individual LDR_ZXI/STR_ZXI
instructions in AArch64ExpandPseudoInsts.
Patch by Sander de Smalen.
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D75988
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions