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| author | S. VenkataKeerthy <31350914+svkeerthy@users.noreply.github.com> | 2025-10-07 13:45:20 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-07 13:45:20 -0700 |
| commit | 879f8616ef93b5f3732568aeabdade6af26094f7 (patch) | |
| tree | 2062350e631b8e0ce6e11117d1c8f35fcc897b2b /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 47820b1260b4f3282792e89a42272758c777c51c (diff) | |
| download | llvm-879f8616ef93b5f3732568aeabdade6af26094f7.zip llvm-879f8616ef93b5f3732568aeabdade6af26094f7.tar.gz llvm-879f8616ef93b5f3732568aeabdade6af26094f7.tar.bz2 | |
[IR2Vec] Initial infrastructure for MIR2Vec (#161463)
This PR introduces the initial infrastructure and vocabulary necessary for generating embeddings for MIR (discussed briefly in the earlier IR2Vec RFC - https://discourse.llvm.org/t/rfc-enhancing-mlgo-inlining-with-ir2vec-embeddings). The MIR2Vec embeddings are useful in driving target specific optimizations that work on MIR like register allocation.
(Tracking issue - #141817)
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
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