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| author | Rajat Bajpai <rbajpai@nvidia.com> | 2025-10-31 18:54:43 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-31 18:54:43 +0530 |
| commit | 7b29b49c3e47a1616127bd08ceee3459866430b4 (patch) | |
| tree | 3f8500a0c9cd557703fca494b3ca24f4a5cab429 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 0ed8e66f88b689c152245d6b968a06fa8e67b51f (diff) | |
| download | llvm-7b29b49c3e47a1616127bd08ceee3459866430b4.zip llvm-7b29b49c3e47a1616127bd08ceee3459866430b4.tar.gz llvm-7b29b49c3e47a1616127bd08ceee3459866430b4.tar.bz2 | |
[NVPTX] Move TMA G2S lowering to Tablegen (#165710)
This change refactors G2S TMA implementation to use pure TableGen based
expansion instead verbose ISel DAG expansion. In addition, it adds
proper arch predicates for TMA G2S.
All the test cases are validated locally with CUDA 13.0 toolkit.
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions