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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2022-11-02 18:50:48 -0700 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2023-01-24 17:55:11 -0400 |
| commit | 778cf5431cafc243f81dd5c8cbd27701ff7f9120 (patch) | |
| tree | 1a1c63468df1436efd906da8f33afcb033e77e2a /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | e44a305690add9f759d2fba85827bca260c94b41 (diff) | |
| download | llvm-778cf5431cafc243f81dd5c8cbd27701ff7f9120.zip llvm-778cf5431cafc243f81dd5c8cbd27701ff7f9120.tar.gz llvm-778cf5431cafc243f81dd5c8cbd27701ff7f9120.tar.bz2 | |
IR: Add atomicrmw uinc_wrap and udec_wrap
These are essentially add/sub 1 with a clamping value.
AMDGPU has instructions for these. CUDA/HIP expose these as
atomicInc/atomicDec. Currently we use target intrinsics for these,
but those do no carry the ordering and syncscope. Add these to
atomicrmw so we can carry these and benefit from the regular
legalization processes.
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
| -rw-r--r-- | llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp index 26994b1..f85fd86 100644 --- a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp +++ b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp @@ -604,6 +604,10 @@ static unsigned getEncodedRMWOperation(AtomicRMWInst::BinOp Op) { case AtomicRMWInst::FSub: return bitc::RMW_FSUB; case AtomicRMWInst::FMax: return bitc::RMW_FMAX; case AtomicRMWInst::FMin: return bitc::RMW_FMIN; + case AtomicRMWInst::UIncWrap: + return bitc::RMW_UINC_WRAP; + case AtomicRMWInst::UDecWrap: + return bitc::RMW_UDEC_WRAP; } } |