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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-07-18 14:23:10 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-07-18 14:23:10 +0000 |
| commit | 748d3efec6e14c75068c90d5439df243b39b1edb (patch) | |
| tree | 901c8862cd1de7f64b90b80852b411b3b66ce7f1 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | d80f626568544e8ad041ac24076a589da27dd83d (diff) | |
| download | llvm-748d3efec6e14c75068c90d5439df243b39b1edb.zip llvm-748d3efec6e14c75068c90d5439df243b39b1edb.tar.gz llvm-748d3efec6e14c75068c90d5439df243b39b1edb.tar.bz2 | |
[Hexagon] Fix zero latency instructions with multiple predecessors
An instruction may have multiple predecessors that are candidates
for using .cur. However, only one of them can use .cur in the
packet. When this case occurs, we need to make sure that only
one of the dependences gets a 0 latency value.
Patch by Brendon Cahoon.
llvm-svn: 275790
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions