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| author | Piyou Chen <piyou.chen@sifive.com> | 2024-11-25 12:43:39 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-25 12:43:39 +0800 |
| commit | 7317a6e99026f65a343e2e69685445dc5bd83172 (patch) | |
| tree | 88c676d8139e980bdb4213f8ad528950655b7818 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 2523439021dedbaee1ddfc49f59deab43cf6bb9b (diff) | |
| download | llvm-7317a6e99026f65a343e2e69685445dc5bd83172.zip llvm-7317a6e99026f65a343e2e69685445dc5bd83172.tar.gz llvm-7317a6e99026f65a343e2e69685445dc5bd83172.tar.bz2 | |
[RISCV][MachineVerifier] Use RegUnit for register liveness checking (#115980)
For the RISC-V target, V14_V15 are not subregisters of v14m4, even
though they share some registers. Currently, the MachineVerifier reports
an error when checking register liveness for segment load/store
operations.
This patch adds additional register liveness checking, using RegUnit
instead of subregisters, to prevent this error.
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions