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| author | David Stuttard <david.stuttard@amd.com> | 2021-04-30 11:37:41 +0100 |
|---|---|---|
| committer | David Stuttard <david.stuttard@amd.com> | 2021-05-14 09:25:44 +0100 |
| commit | 72d570ca085c809edd70d355cad7129092afbf90 (patch) | |
| tree | cb6c7cb80309ef79273cf1204d8c1ece88b3539a /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 2db090a2ebd76f120bfae4fbe4b7241667aa585e (diff) | |
| download | llvm-72d570ca085c809edd70d355cad7129092afbf90.zip llvm-72d570ca085c809edd70d355cad7129092afbf90.tar.gz llvm-72d570ca085c809edd70d355cad7129092afbf90.tar.bz2 | |
[AMDGPU][AsmParser/Disassembler] Correct A16 and G16 handling
A16 support for image instructions assembly/disassembly (gfx10) was missing
Also refactor MIMG op addr size calcs to common function
We'd got 3 places where the same operation was being done.
One test is now marked XFAIL until a related codegen patch is in place
Differential Revision: https://reviews.llvm.org/D102231
Change-Id: I7e86e730ef8c71901457855cba570581f4f576bb
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions