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| author | Zakk Chen <zakk.chen@sifive.com> | 2020-12-28 08:44:38 -0800 |
|---|---|---|
| committer | Zakk Chen <zakk.chen@sifive.com> | 2020-12-29 16:50:53 -0800 |
| commit | 6da00336248ca725f5f817337e8486c234ace187 (patch) | |
| tree | 29ec5e4085caab4bfa1b8990d371b626751775fa /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 57b8afda10b620c7b576af0606cbbcd1c7b64a8a (diff) | |
| download | llvm-6da00336248ca725f5f817337e8486c234ace187.zip llvm-6da00336248ca725f5f817337e8486c234ace187.tar.gz llvm-6da00336248ca725f5f817337e8486c234ace187.tar.bz2 | |
[RISCV] Define vsext/vzext intrinsics.
Define vsext/vzext intrinsics.and lower to V instructions.
Define new fraction register class fields in LMULInfo and a
NoReg to present invalid LMUL register classes.
Authored-by: ShihPo Hung <shihpo.hung@sifive.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D93893
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions