diff options
| author | Luo, Yuanke <yuanke.luo@intel.com> | 2022-10-20 17:49:47 +0800 |
|---|---|---|
| committer | Luo, Yuanke <yuanke.luo@intel.com> | 2022-10-21 17:01:20 +0800 |
| commit | 6ade6d25110f9dbe8c7fb2f8ce6af951a3c23bc2 (patch) | |
| tree | 9abef2dd339fbb0c72339300c2f2cce6e0d37b73 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 67902920628f889cdef402bb0e8ca7a3df51e25f (diff) | |
| download | llvm-6ade6d25110f9dbe8c7fb2f8ce6af951a3c23bc2.zip llvm-6ade6d25110f9dbe8c7fb2f8ce6af951a3c23bc2.tar.gz llvm-6ade6d25110f9dbe8c7fb2f8ce6af951a3c23bc2.tar.bz2 | |
[Verifier] Relieve intrinsics parameter alignment size constrain
In D121898 we restrict parameter alignment size in IR since DAGISel
only have 4 bits to hold the alignment value. However intrinsics
won't be lowered to call instruction, so we can remove the constrain
for intrinsics.
Differential Revision: https://reviews.llvm.org/D136330
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions