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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2021-05-24 18:26:16 +0100 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2021-05-25 11:35:57 +0100 |
| commit | 68ef68f8ac5cad1fdcd9c7b0e2a8f134d9f595ae (patch) | |
| tree | c938805bdde9d054b60b399fbebe6f35c18cd6d5 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | e3b8e6d48251a3b85f925fe695ef961013ddb940 (diff) | |
| download | llvm-68ef68f8ac5cad1fdcd9c7b0e2a8f134d9f595ae.zip llvm-68ef68f8ac5cad1fdcd9c7b0e2a8f134d9f595ae.tar.gz llvm-68ef68f8ac5cad1fdcd9c7b0e2a8f134d9f595ae.tar.bz2 | |
[CostModel][X86] Improve accuracy of vXi8/vXi16 vector non-uniform shift costs on AVX2/AVX512 targets
Determined from llvm-mca analysis, AVX2+ capable targets have a higher throughput for VPBLENDVB and VPMOVZX ops, making it cheaper to perform shift+select patterns for vXi8 shifts or extend/shift/truncate for vXi16 shifts. Similarly AVX512BW can perform vXi8 as extend/shift/truncate patterns.
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions