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| author | Quinn Pham <Quinn.Pham@ibm.com> | 2021-09-16 14:00:01 -0500 |
|---|---|---|
| committer | Quinn Pham <Quinn.Pham@ibm.com> | 2021-09-27 12:36:18 -0500 |
| commit | 682e15f371db9b515d95fe9571983f1070bbc805 (patch) | |
| tree | 61eb1b1b8c289847fdfe72a3064336fb4f9a298a /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | c4afb5f81b62b903e4af8a92235e1b901e184040 (diff) | |
| download | llvm-682e15f371db9b515d95fe9571983f1070bbc805.zip llvm-682e15f371db9b515d95fe9571983f1070bbc805.tar.gz llvm-682e15f371db9b515d95fe9571983f1070bbc805.tar.bz2 | |
[PowerPC] Fix td pattern for P10 VSLDBI and VSRDBI
This patch fixes the pattern for the P10 instructions Vector Shift Left
Double by Bit Immediate VN-form and Vector Shift Right Double by Bit
Immediate VN-form. The third argument should be a target constant (`timm`)
instead of an `i32` because an immediate is expected.
Reviewed By: lei
Differential Revision: https://reviews.llvm.org/D109920
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions