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| author | KAWASHIMA Takahiro <t-kawashima@fujitsu.com> | 2022-12-12 14:25:31 +0900 |
|---|---|---|
| committer | KAWASHIMA Takahiro <t-kawashima@fujitsu.com> | 2022-12-20 23:47:51 +0900 |
| commit | 673b4ad64577e3336cb8109869919b21341e0d74 (patch) | |
| tree | ad46f7e4608b713f01bb6f21a96f19f7c460eb3d /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 4ac51dd53d93b8dd18c58093766483c657fe3a08 (diff) | |
| download | llvm-673b4ad64577e3336cb8109869919b21341e0d74.zip llvm-673b4ad64577e3336cb8109869919b21341e0d74.tar.gz llvm-673b4ad64577e3336cb8109869919b21341e0d74.tar.bz2 | |
[AArch64] Add FP16 instructions to isAssociativeAndCommutative
`-mcpu=` in `llvm/test/CodeGen/AArch64/machine-combiner.ll` is changed
to `neoverse-n2` to use FP16 and SVE/SVE2 instructions. By this, the
register allocation and/or instruction scheduling are slightly changed
and some existing `CHECK` lines need to be updated.
Differential Revision: https://reviews.llvm.org/D139809
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions