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| author | Craig Topper <craig.topper@gmail.com> | 2016-12-06 08:07:58 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2016-12-06 08:07:58 +0000 |
| commit | 5fc7bc91f9ad23b1ec1471186ff0603369ca6563 (patch) | |
| tree | 7c6fe220bf402b35db4a8745d2caa8592732da22 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 4facc13108b9ae57caed8690ee4185387cf4d0fb (diff) | |
| download | llvm-5fc7bc91f9ad23b1ec1471186ff0603369ca6563.zip llvm-5fc7bc91f9ad23b1ec1471186ff0603369ca6563.tar.gz llvm-5fc7bc91f9ad23b1ec1471186ff0603369ca6563.tar.bz2 | |
[X86] Correct pattern for VSQRTSSr_Int, VSQRTSDr_Int, VRCPSSr_Int, and VRSQRTSSr_Int to not have an IMPLICIT_DEF on the first input. The semantics of the intrinsic are clear and not undefined.
The intrinsic takes one argument, the lower bits are affected by the operation and the upper bits should be passed through. The instruction itself takes two operands, the high bits of the first operand are passed through and the low bits of the second operand are modified by the operation. To match this to the intrinsic we should pass the single intrinsic input to both operands.
I had to remove the stack folding test for these instructions since they depended on the incorrect behavior. The same register is now used for both inputs so the load can't be folded.
llvm-svn: 288779
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions