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| author | Craig Topper <craig.topper@sifive.com> | 2021-02-11 09:22:25 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-02-11 09:43:13 -0800 |
| commit | 5744502a137cbc9f2732e707fde984399b241515 (patch) | |
| tree | dc467d2778879f7e49f444faafc872210d7c776a /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 0557b1bdec6e5e7228292f390a49829efcacd4da (diff) | |
| download | llvm-5744502a137cbc9f2732e707fde984399b241515.zip llvm-5744502a137cbc9f2732e707fde984399b241515.tar.gz llvm-5744502a137cbc9f2732e707fde984399b241515.tar.bz2 | |
[TargetLowering][RISCV][AArch64][PowerPC] Enable BuildUDIV/BuildSDIV on illegal types before type legalization if we can find a larger legal type that supports MUL.
If we wait until the type is legalized, we'll lose information
about the orginal type and need to use larger magic constants.
This gets especially bad on RISCV64 where i64 is the only legal
type.
I've limited this to simple scalar types so it only works for
i8/i16/i32 which are most likely to occur. For more odd types
we might want to do a small promotion to a type where MULH is legal
instead.
Unfortunately, this does prevent some urem/srem+seteq matching since
that still require legal types.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D96210
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
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