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| author | Kunqiu Chen <camsyn@foxmail.com> | 2025-10-31 21:04:35 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-31 21:04:35 +0800 |
| commit | 511c9c064804e86eaad5f1df4b67e6474639f434 (patch) | |
| tree | 75172cd1ee3d42a4d5f758802aaa5debbe9237f3 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 2108c623e618265c4146c405f196953a9c157e73 (diff) | |
| download | llvm-511c9c064804e86eaad5f1df4b67e6474639f434.zip llvm-511c9c064804e86eaad5f1df4b67e6474639f434.tar.gz llvm-511c9c064804e86eaad5f1df4b67e6474639f434.tar.bz2 | |
[UTC] Support to test annotated IR (#165419)
Some analysis/transformation, e.g., predicate info/ mem ssa, insert
instruction annotations as comments, referring to
https://github.com/llvm/llvm-project/pull/165249#discussion_r2466200672.
This PR makes UTC support checking these instruction annotations with an
extra UTC option `-check-inst-comments`.
E.g.,
Before:
```LLVM
; CHECK: [[Z_0:%.*]] = bitcast i1 [[Z]] to i1
```
After:
```LLVM
; CHECK-NEXT: ; branch predicate info { TrueEdge: 0 Comparison: [[Z]] = and i1 [[XZ]], [[YZ]] Edge: [label [[TMP0:%.*]],label %nope], RenamedOp: [[Z]] }
; CHECK-NEXT: [[Z_0:%.*]] = bitcast i1 [[Z]] to i1
```
This PR also regenerates all UTC-generated tests for PredicateInfo; No
MemSSA test is updated, as there are no UTC-generated tests designated
for `print<memoryssa>`.
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions