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| author | Craig Topper <craig.topper@intel.com> | 2017-08-19 23:21:22 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-08-19 23:21:22 +0000 |
| commit | 4de6f583da6e0c1367f192f2af2b53fb040021e9 (patch) | |
| tree | 73a88be2a3f7f991fd5b221b2858638996600f59 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | afa69eecbb4a6d80d20f09b62abac23c6b6b8293 (diff) | |
| download | llvm-4de6f583da6e0c1367f192f2af2b53fb040021e9.zip llvm-4de6f583da6e0c1367f192f2af2b53fb040021e9.tar.gz llvm-4de6f583da6e0c1367f192f2af2b53fb040021e9.tar.bz2 | |
[X86] Merge all of the vecload and alignedload predicates into single predicates.
We can load the memory VT and check for natural alignment. This also adds a new preferNonTemporalLoad helper that checks the correct subtarget feature based on the load size.
This shrinks the isel table by at least 5000 bytes by allowing more reordering and combining to occur.
llvm-svn: 311266
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions