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| author | Mark Searles <m.c.searles@gmail.com> | 2018-02-19 16:42:49 +0000 |
|---|---|---|
| committer | Mark Searles <m.c.searles@gmail.com> | 2018-02-19 16:42:49 +0000 |
| commit | 419bdab7595ff213c326f40683b1dca78c5fff03 (patch) | |
| tree | 3d364c7700c810b7cabe7961904561039ef056dd /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | bc35f069f4c88d355488466f9c2d7953c9202168 (diff) | |
| download | llvm-419bdab7595ff213c326f40683b1dca78c5fff03.zip llvm-419bdab7595ff213c326f40683b1dca78c5fff03.tar.gz llvm-419bdab7595ff213c326f40683b1dca78c5fff03.tar.bz2 | |
[AMDGPU] Increased vector length for global/constant loads.
Summary: GCN ISA supports instructions that can read 16 consecutive dwords from memory through the scalar data cache; loadstoreVectorizer should take advantage of the wider vector length and pack 16/8 elements of dwords/quadwords.
Author: FarhanaAleen
Reviewed By: rampitec
Subscribers: llvm-commits, AMDGPU
Differential Revision: https://reviews.llvm.org/D43275
llvm-svn: 325518
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions