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authorMin-Yih Hsu <min.hsu@sifive.com>2025-10-07 14:30:27 -0700
committerGitHub <noreply@github.com>2025-10-07 14:30:27 -0700
commit30b9ef8088c35d86fbdffebe0ba8cdcea1afe6eb (patch)
tree61b90068744da98d212e53a731b6b7e22d2ff63e /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
parent5c613f287df7fc94e159621f870f1bb1fe3baaee (diff)
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[RISCV] Factor out the core part of LMULWriteResMXVariant. NFC (#162347)
LMULWriteResMXVariant is a helper class that makes creating LMUL-aware `SchedVar` easier. In preparation for later patches that require - LMUL- _and_ SEW-aware `SchedVar` - Assign different processor resources for predicated and non-predicated variants I factor out the core logics of LMULWriteResMXVariant into another impl class, such that it'll be easier to add _"LMULSEWWriteResMXSEWVariant"_ easier later. I also extend this class so that users can customize processor resources for the non-predicated variant. Despite these, this patch is still a NFC. I thought it'll be cleaner not to mix the changes here into later patches.
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