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author | Chad Rosier <mcrosier@codeaurora.org> | 2016-05-11 20:19:54 +0000 |
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committer | Chad Rosier <mcrosier@codeaurora.org> | 2016-05-11 20:19:54 +0000 |
commit | 23a1a9a66d50f073b8817ebb05777249421681a8 (patch) | |
tree | 855a777a55d06b4d2b2b9828f9aefd2b18c2b631 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
parent | c610da6174876e2b54ff0a7eb6eec15324d6b88d (diff) | |
download | llvm-23a1a9a66d50f073b8817ebb05777249421681a8.zip llvm-23a1a9a66d50f073b8817ebb05777249421681a8.tar.gz llvm-23a1a9a66d50f073b8817ebb05777249421681a8.tar.bz2 |
[AArch64] Improve getUsefulBitsForUse for narrow stores.
For narrow stores (e.g., strb, srth) we know the upper bits of the register are
unused/not useful. In some cases we can use this information to eliminate
unnecessary instructions.
For example, without this patch we generate (from the 2nd test case):
ldr w8, [x0]
and w8, w8, #0xfff0
bfxil w8, w2, #16, #4
strh w8, [x1]
and after the patch the 'and' is removed:
ldr w8, [x0]
bfxil w8, w2, #16, #4
strh w8, [x1]
ret
During the lowering of the bitfield insert instruction the 'and' is eliminated
because we know the upper 16-bits that are masked off are unused and the lower
4-bits that are masked off are overwritten by the insert itself. Therefore, the
'and' is unnecessary.
Differential Revision: http://reviews.llvm.org/D20175
llvm-svn: 269226
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions