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| author | Jessica Paquette <jpaquette@apple.com> | 2021-08-26 11:04:17 -0700 |
|---|---|---|
| committer | Jessica Paquette <jpaquette@apple.com> | 2021-08-26 11:45:11 -0700 |
| commit | 2363a2000171d12e21bc49a783291401656c4f35 (patch) | |
| tree | 680b64c264e1d20320c470e196073102949efece /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 9b9e7f6f4e05baa99a795e0cce60ba86091acc9a (diff) | |
| download | llvm-2363a2000171d12e21bc49a783291401656c4f35.zip llvm-2363a2000171d12e21bc49a783291401656c4f35.tar.gz llvm-2363a2000171d12e21bc49a783291401656c4f35.tar.bz2 | |
[AArch64][GlobalISel] Optimize G_BUILD_VECTOR of undef + 1 elt -> SUBREG_TO_REG
This pattern
```
%elt = ... something ...
%undef = G_IMPLICIT_DEF
%vec = G_BUILD_VECTOR %elt, %undef, %undef, ... %undef
```
Can be selected to a SUBREG_TO_REG, assuming `%elt` and `%vec` have the same
register bank. We don't care about any of the bits in `%vec` aside from those
in `%elt`, which just happens to be the 0th element.
This is preferable to emitting `mov` instructions for every index.
This gives minor code size improvements on the test suite at -Os.
Differential Revision: https://reviews.llvm.org/D108773
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions