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| author | alex-t <alexander.timofeev@amd.com> | 2021-12-20 19:03:13 +0300 |
|---|---|---|
| committer | alex-t <alexander.timofeev@amd.com> | 2021-12-20 20:53:48 +0300 |
| commit | 19727e31fb2c0e0b27bd8583d8bda1a42e6d41f8 (patch) | |
| tree | 8391e8e9d1ab89325fa24417745e9f2e1c73842a /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 4fe5543b3c3e9662b0adf4f10b2d18dcd5ceb2d7 (diff) | |
| download | llvm-19727e31fb2c0e0b27bd8583d8bda1a42e6d41f8.zip llvm-19727e31fb2c0e0b27bd8583d8bda1a42e6d41f8.tar.gz llvm-19727e31fb2c0e0b27bd8583d8bda1a42e6d41f8.tar.bz2 | |
[AMDGPU] Enable divergence predicates for ctlz/cttz
ctlz/cttz get lowered to the set of target opcodes
This change enables the ISel to select SALU or VALU form according to the SDNode divergence.
CTLZ - S_FLBIT_I32_B32 if uniform and V_FFBH_U32_e64 if divergent
CTTZ - S_FF1_I32_B32 if uniform and V_FFBL_B32_e64 if divergent
Also @llvm.amdgcn.sffbh.i32 gets lowered to S_FLBIT_I32 if uniform and V_FFBH_I32_e64 if divergent
NOTE: 64bit versions S_FF1_I32_B64 and S_FLBIT_I32_B64 are not currently supported by the DAG ISel.
ctlz/cttz with i64 input are split into two 32bit instructions. Nevertheless, they already have the patterns
and were equipped with the divergence predicates to make sure they will be selected correctly when enabled.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D116044
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions