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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-15 19:44:07 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-15 19:44:07 +0000 |
| commit | 18b7133843bdfdfbad0f981c8cce944426e8411c (patch) | |
| tree | ff1f040e0b2179f508b82318939fdca46e74e36c /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 6ed315f89be1b5e692b1d8e2f5ddda08d5b4e47d (diff) | |
| download | llvm-18b7133843bdfdfbad0f981c8cce944426e8411c.zip llvm-18b7133843bdfdfbad0f981c8cce944426e8411c.tar.gz llvm-18b7133843bdfdfbad0f981c8cce944426e8411c.tar.bz2 | |
AMDGPU/GlobalISel: Fix handling of sgpr (not scc bank) s1 to VCC
This was emitting a copy from a 32-bit register to a 64-bit.
llvm-svn: 366117
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions