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| author | Thomas Raoux <thomasraoux@google.com> | 2022-05-09 17:18:21 +0000 |
|---|---|---|
| committer | Thomas Raoux <thomasraoux@google.com> | 2022-05-10 22:30:24 +0000 |
| commit | 15bcc36eede13b24470e554dfa932f1fc40dd4ba (patch) | |
| tree | 8f77c0a55b7713ae90ed1035d480462d8b610d78 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 71bcead98b2e655031208e5ad0ce89f8971a6343 (diff) | |
| download | llvm-15bcc36eede13b24470e554dfa932f1fc40dd4ba.zip llvm-15bcc36eede13b24470e554dfa932f1fc40dd4ba.tar.gz llvm-15bcc36eede13b24470e554dfa932f1fc40dd4ba.tar.bz2 | |
[mlir][gpu] Move async copy ops to NVGPU and add caching hints
Move async copy operations to NVGPU as they only exist on NV target and are
designed to match ptx semantic. This allows us to also add more fine grain
caching hint attribute to the op.
Add hint to bypass L1 and hook it up to NVVM op.
Differential Revision: https://reviews.llvm.org/D125244
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions