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| author | Amara Emerson <amara@apple.com> | 2021-06-26 23:36:46 -0700 |
|---|---|---|
| committer | Amara Emerson <amara@apple.com> | 2021-07-02 12:31:21 -0700 |
| commit | 0111da2ef80adc516f13d7c7f4125eb9eea6c08f (patch) | |
| tree | c4f30e93e1a0a3e88ea74cc44251722de3c93fd2 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 53fef0b2933a120b2ee876127c574002f8eb8c14 (diff) | |
| download | llvm-0111da2ef80adc516f13d7c7f4125eb9eea6c08f.zip llvm-0111da2ef80adc516f13d7c7f4125eb9eea6c08f.tar.gz llvm-0111da2ef80adc516f13d7c7f4125eb9eea6c08f.tar.bz2 | |
[GlobalISel] Add re-association combine for G_PTR_ADD to allow better addressing mode usage.
We're trying to match a few pointer computation patterns here for
re-association opportunities.
1) Isolating a constant operand to be on the RHS, e.g.:
G_PTR_ADD(BASE, G_ADD(X, C)) -> G_PTR_ADD(G_PTR_ADD(BASE, X), C)
2) Folding two constants in each sub-tree as long as such folding
doesn't break a legal addressing mode.
G_PTR_ADD(G_PTR_ADD(BASE, C1), C2) -> G_PTR_ADD(BASE, C1+C2)
AArch64 code size improvements on CTMark with -Os:
Program before after diff
pairlocalalign 251048 251044 -0.0%
consumer-typeset 421820 421812 -0.0%
kc 431348 431320 -0.0%
SPASS 413404 413300 -0.0%
clamscan 384396 384220 -0.0%
tramp3d-v4 370640 370412 -0.1%
lencod 432096 431772 -0.1%
bullet 479400 478796 -0.1%
sqlite3 288504 288072 -0.1%
7zip-benchmark 573796 570768 -0.5%
Geomean difference -0.1%
Differential Revision: https://reviews.llvm.org/D105069
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions