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| author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2017-06-15 17:34:42 +0000 |
|---|---|---|
| committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2017-06-15 17:34:42 +0000 |
| commit | ae9312c487c6178a538e9123700b15558e10ad79 (patch) | |
| tree | 045e605683ac2bf0ec04acddf201b6d20a224623 /llvm/lib/Bitcode/Writer/BitWriter.cpp | |
| parent | 6ec5a63073452f1e6b7970d272d72a800ea066b4 (diff) | |
| download | llvm-ae9312c487c6178a538e9123700b15558e10ad79.zip llvm-ae9312c487c6178a538e9123700b15558e10ad79.tar.gz llvm-ae9312c487c6178a538e9123700b15558e10ad79.tar.bz2 | |
ISel: Fix FastISel of swifterror values
The code assumed that we process instructions in basic block order. FastISel
processes instructions in reverse basic block order. We need to pre-assign
virtual registers before selecting otherwise we get def-use relationships wrong.
This only affects code with swifterror registers.
rdar://32659327
llvm-svn: 305484
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitWriter.cpp')
0 files changed, 0 insertions, 0 deletions