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| author | Florian Hahn <florian.hahn@arm.com> | 2017-06-15 09:31:23 +0000 |
|---|---|---|
| committer | Florian Hahn <florian.hahn@arm.com> | 2017-06-15 09:31:23 +0000 |
| commit | 0a26d2c298a6a493945adf131596dbbfc4a1d216 (patch) | |
| tree | 7bfbf8c3d01c5a7642458cf794a52cc64f4846ab /llvm/lib/Bitcode/Writer/BitWriter.cpp | |
| parent | d07825404971669f6877cd5097cb19bd60e62288 (diff) | |
| download | llvm-0a26d2c298a6a493945adf131596dbbfc4a1d216.zip llvm-0a26d2c298a6a493945adf131596dbbfc4a1d216.tar.gz llvm-0a26d2c298a6a493945adf131596dbbfc4a1d216.tar.bz2 | |
[AArch64] Enable FeatureFuseAES for the generic processor model.
Summary:
Scheduling AESE/AESMC and AESD/AESIMC instruction pairs back-to-back
gives a double digit speedup on benchmarks using those instructions on
Cortex-A processors. In GCC, this optimization is part of the generic
processor model as well.
This change should not have a major performance impact on processors
that do not optimize AES instruction pairs, although I only had access
to Cortex-A processors for benchmarking.
Reviewers: rengolin, kristof.beyls, javed.absar, evandro, silviu.baranga, MatzeB, mcrosier, joelkevinjones, joel_k_jones, bmakam, t.p.northover
Reviewed By: evandro
Subscribers: sbaranga, aemerson, llvm-commits
Differential Revision: https://reviews.llvm.org/D33836
llvm-svn: 305457
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitWriter.cpp')
0 files changed, 0 insertions, 0 deletions