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| author | LemonBoy <thatlemon@gmail.com> | 2021-03-05 16:01:45 +0100 |
|---|---|---|
| committer | LemonBoy <thatlemon@gmail.com> | 2021-03-05 16:09:37 +0100 |
| commit | 8725b24c6d4abaa97425e704652a13dacb35fe3f (patch) | |
| tree | 82e28d2653b63d55eb6715c81f4bd769bbd35175 /llvm/lib/Bitcode/Reader/MetadataLoader.cpp | |
| parent | 5fedf30748381ad84697291591dab7d570f50d06 (diff) | |
| download | llvm-8725b24c6d4abaa97425e704652a13dacb35fe3f.zip llvm-8725b24c6d4abaa97425e704652a13dacb35fe3f.tar.gz llvm-8725b24c6d4abaa97425e704652a13dacb35fe3f.tar.bz2 | |
[AArch64] Legalize horizontal fmax/fmin reductions on f16 vectors
Expand the horizontal reduction during the instruction selection phase, but only if the target doesn't support the full fp16 instruction set.
Fixes https://bugs.llvm.org/show_bug.cgi?id=49401
Reviewed By: aemerson
Differential Revision: https://reviews.llvm.org/D97840
Diffstat (limited to 'llvm/lib/Bitcode/Reader/MetadataLoader.cpp')
0 files changed, 0 insertions, 0 deletions