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authorMin-Yih Hsu <min.hsu@sifive.com>2024-11-06 14:53:42 -0800
committerGitHub <noreply@github.com>2024-11-06 14:53:42 -0800
commit7ef7c0d036fb4f37e4a33932c4c0e40714b39fb4 (patch)
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[RISCV] Refine vector division latencies in SiFive P600's scheduling model (#115038)
For both vector integer and floating point divisions. Co-authored-by: Yeting Kuo <yeting.kuo@sifive.com>
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