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| author | David Green <david.green@arm.com> | 2019-07-13 15:43:00 +0000 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2019-07-13 15:43:00 +0000 |
| commit | 458a720ec17234f01d6e92e557436187e6f32c4b (patch) | |
| tree | 0e119be795f643261ea5e571cb8f81eb6ab192d3 /llvm/lib/Bitcode/Reader/MetadataLoader.cpp | |
| parent | f6ce7ddecbc593a3911eb119f84e4b437aad8536 (diff) | |
| download | llvm-458a720ec17234f01d6e92e557436187e6f32c4b.zip llvm-458a720ec17234f01d6e92e557436187e6f32c4b.tar.gz llvm-458a720ec17234f01d6e92e557436187e6f32c4b.tar.bz2 | |
[ARM] Add sign and zero extend patterns for MVE
The vmovlb instructions can be uses to sign or zero extend vector registers
between types. This adds some patterns for them and relevant testing. The
VBICIMM generation is also put behind a hasNEON check (as is already done for
VORRIMM).
Code originally by David Sherwood.
Differential Revision: https://reviews.llvm.org/D64069
llvm-svn: 366008
Diffstat (limited to 'llvm/lib/Bitcode/Reader/MetadataLoader.cpp')
0 files changed, 0 insertions, 0 deletions