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| author | Craig Topper <craig.topper@sifive.com> | 2024-05-28 15:54:44 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-05-28 15:54:44 -0700 |
| commit | f7c8a0339c64810a3c1b28d9b3b20e02a2be6232 (patch) | |
| tree | 4de33666c10847a6d7d3bc874ac1f230bd2b8c70 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 760c2aa55f0c5f56bed944328b23aa3f2f764346 (diff) | |
| download | llvm-f7c8a0339c64810a3c1b28d9b3b20e02a2be6232.zip llvm-f7c8a0339c64810a3c1b28d9b3b20e02a2be6232.tar.gz llvm-f7c8a0339c64810a3c1b28d9b3b20e02a2be6232.tar.bz2 | |
[RISCV] Combine vXi32 (mul (and (lshr X, 15), 0x10001), 0xffff) -> (bitcast (sra (v2Xi16 (bitcast X)), 15)) (#93565)
Similar for i16 and i64 elements for both fixed and scalable vectors.
This reduces the number of vector instructions, but increases vl/vtype
toggles.
This reduces some code in 525.x264_r from SPEC2017. In that usage, the
vectors are fixed with a small number of elements so vsetivli can be
used.
This is similar to `performMulVectorCmpZeroCombine` from AArch64.
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions