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| author | Jirui Wu <jirui.wu@arm.com> | 2023-01-31 10:11:24 +0000 |
|---|---|---|
| committer | Jirui Wu <jirui.wu@arm.com> | 2023-02-24 09:55:35 +0000 |
| commit | ee737ad30fa22256e609279184214f75441acefd (patch) | |
| tree | c732af808df0e7a341b87326435389233b490537 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | e6e753d173db14bb1273db65387dec696b7d7a48 (diff) | |
| download | llvm-ee737ad30fa22256e609279184214f75441acefd.zip llvm-ee737ad30fa22256e609279184214f75441acefd.tar.gz llvm-ee737ad30fa22256e609279184214f75441acefd.tar.bz2 | |
[ARM] Accept .w suffixes for some memory instructions
Some memory instructions in the following sections of Armv7-M ARM allow
the .w mnemonic suffix, even though the preferred disassembly is without
the suffix.
A7.7.46 LDRB (immediate) T3
A7.7.55 LDRH (immediate) T3
A7.7.59 LDRSB (immediate) T2
A7.7.63 LDRSH (immediate) T2
A7.7.163 STRB (immediate) T3
A7.7.170 STRH (immediate) T3
This patch accepts the .w suffixes for theses instructions.
Pseudo-instructions and custom parsing logic are used instead of simple
aliases. More discussions are in these relevant patches:
https://reviews.llvm.org/D68916
https://reviews.llvm.org/D96632
Differential Revision: https://reviews.llvm.org/D142980
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions