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| author | Tim Northover <tnorthover@apple.com> | 2015-02-24 17:22:34 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2015-02-24 17:22:34 +0000 |
| commit | e95c5b3236cf43cee9f8ea793adbe9cc86f262c3 (patch) | |
| tree | 20197394da09f3d8b8dd907edb8fcde1c5ba8b6a /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 2cc248e2c98ee361ebc7767338eb947d97609486 (diff) | |
| download | llvm-e95c5b3236cf43cee9f8ea793adbe9cc86f262c3.zip llvm-e95c5b3236cf43cee9f8ea793adbe9cc86f262c3.tar.gz llvm-e95c5b3236cf43cee9f8ea793adbe9cc86f262c3.tar.bz2 | |
ARM: treat [N x i32] and [N x i64] as AAPCS composite types
The logic is almost there already, with our special homogeneous aggregate
handling. Tweaking it like this allows front-ends to emit AAPCS compliant code
without ever having to count registers or add discarded padding arguments.
Only arrays of i32 and i64 are needed to model AAPCS rules, but I decided to
apply the logic to all integer arrays for more consistency.
llvm-svn: 230348
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions